Delay circuits employing cascaded delay stages and a selection circuit for re-timing a clock signal with a synchronizing signal are well known and widely used, for example, in video signal synchronizing circuitry. An example is described by Willis et al. in U.S. Pat. No. 4,992,874 entitled METHOD AND APPARATUS FOR CORRECTING TIMING ERRORS AS FOR A MULTI-PICTURE DISPLAY which issued 12 Feb. 1991. Willis et al. describe a skew correction system for a television receiver with picture in picture (PIP) processing. An element of an embodiment of the Willis et al. PIP receiver includes a clock phase shifting circuit which re-times a sampling clock locked to burst of the main picture signal with a horizontal synchronizing signal derived from the picture display processing circuitry.
The present invention is directed to providing certain improvements in clock retiming circuitry of the general type described by Willis et al. to facilitate construction of the re-timing circuitry in an integrated circuit using standard semiconductor processing techniques. To understand the nature of the problems solved by the present invention, it is helpful first to consider an embodiment of the Willis et al. re-timing circuit in some detail. To this end, FIG. 1 herein, labeled "Prior Art" has been drawn based on the Willis et al. patent.
The clock re-timing apparatus 100 of FIG. 1, includes an input terminal 102 for receiving a main clock input signal MCK to be retimed or "edge aligned" with a horizontal synchronizing signal HS. The main clock input signal MCK is coupled via conductor 104 to the input of a tapped delay line 130 comprising 15 delay elements .DELTA.1-.DELTA.15. The delay line taps T1-T15 together with the un-delayed main clock input signal MCK are applied via bus 112 and conductor 104, respectively, to a memory unit 106 comprising fifteen "D" type flip-flops. All flip-flops in the memory unit 106 are clocked simultaneously by the leading edge of a horizontal synchronizing signal HS applied to input terminal 114. As a result, the fifteen flip-flops in memory 106 store what may be thought of as a "snap-shot" or "picture" of all of the delay line tap values at the time the horizontal synchronizing pulse arrives. Since there are 15 delays of, at least, 5 nano-seconds each, the stored tap values represent samples of one complete cycle (e.g., 70 nano-seconds, NTSC assumed) of the clock signal MCK at the instant of arrival of the horizontal synchronizing signal.
By comparing all fifteen tap values stored in flip-flops 106, it can be determined which tap output signal has its edge closest to the leading edge of horizontal sync HS. This identification is made by the multiplex selection logic unit 108 that receives the 15 stored tap values from memory unit 106 via the 15 conductor bus 118. From the 15 input tap delays, unit 108 provides on output signal on the 16 conductor bus 120 which identifies which of the 15 delayed signals at taps T1-T15 or the input signal (non delayed) has an edge or transition that is closest to the edge of horizontal sync signal HS. The closest tap signal, after identification by logic 108, is supplied via the 16 conductor bus 120 to a multiplex selection switch 110. The switch 110 then selects the one of the 15 tap signals (delayed) or the input signal (non-delayed) as an output signal YCK and applies this signal to output terminal 116 for the remainder of the horizontal line.
In the above manner the input master clock signal MCK is delayed by the tap identified by the selection logic unit 106 as being closest to the leading edge of horizontal sync and this tap is used for delaying all following master clock signals for the remainder of the horizontal line. When the next horizontal line begins, the edge of horizontal sync again latches all of the tap delay data in memory 106 and the cycle repeats. Accordingly, the master clock signal MCK is phase shifted by the selected tap delay to produce the phase shifted output clock YCK that is edge aligned with horizontal synchronizing signal HS.